FPGA DIO2 Custom

Navigation:  Targets > TS-ARM I/O >

FPGA DIO2 Custom

 Previous pageReturn to chapter overviewNext page

FPGA DIO2 Custom

 

Warning: All pins on the DIO2 header use 0-3.3V logic levels. Do not drive these lines to 5V.

General purpose IO (GPIO/DIO)

Default all pins are accessible as general purpose pins. If a component is enabled on the same pin, the component claims the pin and the pin is no longer available for general purpose usage.

 

The pins of the 40-pin header mounted at the side of the FPGA can be controlled.

 

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

 

Some pins are not available, because the have a special function:

 

Pin

Function

2

GND

18

OEV (set high by the FPGA, to disable the signals at the VGA connector)

20

5 V

22

GND

40

3.3 V

Available I/O components

1.35 General purpose digital input / output pins

2.5x PWM output

3.5x Frequency generation output (square wave 50% duty) for stepper motor control

4.5x Encoder input

5.4x Duty cycle measurement / Frequency measurement / Edge counter input

 

The 35 general purpose input/output pins are shared with the other components. See the following pin layout table:

 

Pin layout

This is a layout of the 40-pin connector at the side of the FPGA board

 

Function 2

Function 1

Pin

Pin

Function 1

Function 2

PWM2 C /
Frequency2 C

GPIO 1

1

2

GND

PWM2 A /
Frequency2 A

GPIO 3

3

4

GPIO 4

PWM2 B /

Frequency2 B

Count /
Quadrature Enc 2 (Index)

GPIO 5

5

6

GPIO 6

Count /

Quadrature Enc 2 (A)

Count /
Quadrature Enc 2 (B)

GPIO 7

7

8

GPIO 8

Count /

Quadrature Enc 4 (A)

PWM4 A /
Frequency4 A

GPIO 9

9

10

GPIO 10

Count /

Quadrature Enc 4 (B)

PWM4 B /
Frequency4 B

GPIO 11

11

12

GPIO 12

Count /

Quadrature Enc 4 (Index)

PWM4 C /
Frequency4 C

GPIO 13

13

14

GPIO 14

Duty / Frequency /

Edge measurem. 3

PWM5 A /
Frequency5 A

GPIO 15

15

16

GPIO 16

Duty / Frequency /

Edge measurem. 4

PWM5 B /
Frequency5 B

GPIO 17

17

18

OEV

PWM5 C /
Frequency5 C

GPIO 19

19

20

5 V

PWM1 C /
Frequency1 C

GPIO 21

21

22

GND

PWM1 A /
Frequency1 A

GPIO 23

23

24

GPIO 24

PWM1 B /

Frequency1 B

Count /

Quadrature Enc 1 (Index)

GPIO 25

25

26

GPIO 26

Count /

Quadrature Enc 1 (A)

Count /

Quadrature Enc 1 (B)

GPIO 27

27

28

GPIO 28

Count /

Quadrature Enc 3 (A)

PWM3 A /
Frequency3 A

GPIO 29

29

30

GPIO 30

Count /

Quadrature Enc 3 (B)

PWM3 B /
Frequency3 B

GPIO 31

31

32

GPIO 32

Count /

Quadrature Enc 3 (Index)

PWM3 C /
Frequency3 C

GPIO 33

33

34

GPIO 34

Count /
Quadrature Enc 5 (A)

Duty / Frequency /
Edge measurem. 1

GPIO 35

35

36

GPIO 36

RED LED / Count /
Quadrature Enc 5 (B)

Duty / Frequency /
Edge measurem. 2

GPIO 37

37

38

GPIO 38

Green LED / Count /
Quadrature Enc 5 (Index)

 

GPIO 39 (input only)

39

40

3.3 V

 

PWM

The custom-FPGA configuration has 5 PWM outputs.

 

PWM A = Pulse width modulated signal. Frequency = 16 kHz, Duty cycle setpoint resolution 12 bits

PWM B = Direction signal

PWM C = Break signal

Frequency generator / Stepper motor

The custom-FPGA configuration has 5 Frequency outputs.

 

Frequency A = Square wave output. Frequency range: 0-3 MHz, resolution 0.05 Hz, duty cycle 49-51%

Frequency B = Direction signal

Frequency C = Break signal

Encoder

The custom-FPGA configuration has 5 encoder inputs.

 

Encoder channel A = A signal

Encoder channel B = B signal

Encoder index = index signal