FPGA DIO2 Default |
  
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FPGA DIO2 Default |
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Note: The DIO2 port is only the right 20-pin part of the 40 pins FPGA connector. The first 20-pins are used by the VGA output.
The following digital inputs & output are provided
•2 x Quadrature Encoder Input. The Encoder Input can have no reset and a reset on positive or negative index pulse.
•2 x Edge Counter Input. The Edge Counter Input can have no reset and a reset on positive or negative edge.
•8 x Digital Input. Binary input.
•2 X Pulse Width Modulation Output. Pulse Width Modulation output e.g. used to drive a motor via a H-Bridge.
•8 x Digital Output. Binary output.
•2 x LED. Two LED's are present on the board.
There is a 40-pin header next to the FPGA.
It is devided into two 20 pin blocks. One is labeled DIO2 and contains the 18 dedicated GPIO pins. The other contains 17 signals that are used by the VGA output but can also be used as GPIO if video is not used.
Warning: All pins on the DIO2 header use 0-3.3V logic levels. Do not drive these lines to 5V.
2 |
4 |
6 |
8 |
10 |
12 |
14 |
16 |
18 |
20 |
22 |
24 |
26 |
28 |
30 |
32 |
34 |
36 |
38 |
40 |
1 |
3 |
5 |
7 |
9 |
11 |
13 |
15 |
17 |
19 |
21 |
23 |
25 |
27 |
29 |
31 |
33 |
35 |
37 |
39 |
* |
VGA / DIO 3 |
* |
DIO2 |
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pins #2 and #22 are grounds
pin #20 is fused 5V (polyfuse)
pin #40 is regulated 3.3V
pin #18 can be externally driven high to disable DB15 VGA connector DACs
pin #36 and #38 also go to the red and green LEDs (active low)
pin #39 is a dedicated clock input and cannot be programmed for output
Default FPGA configuration Controllab
•Contains VGA / TS XDIO core
Note: Pins 1 to 19 are used for the VGA output and are not available as digital I/O pins.
TS-7300 DIO-2 pin layout
Quadrature counter
Quadrature counter input (2x) no index
Quadrature counter with no reset on index pulse. The counter is initialized on 0 and will count to a maximum of 32767 pulses. If maximum number of pulses is exceeded counter will continue to count from -32768.
Quadrature counter input pins: QUAD?_A and QUAD?_B
Quadrature counter input (2x) reset in positive index
Quadrature counter with reset on positive flank of the index pulse. The counter is initialized on 0 and will count to a maximum of 32767 pulses. If maximum number of pulses is exceeded counter will continue to count from -32768. If a positive index pulse is received the counter will be reset to zero.Quadrature counter input pins: QUAD?_A and QUAD?_B
Index input pin: QUAD?_I
Quadrature counter input (2x) reset in negative index
Quadrature counter with reset on negative flank of the index pulse. The counter is initialized on 0 and will count to a maximum of 32767 pulses. If maximum number of pulses is exceeded counter will continue to count from -32768. If a negative index pulse is received the counter will be reset to zero.
Quadrature counter input pins: QUAD?_A and QUAD?_B
Index input pin: QUAD?_I
Edge counter
Edge counter no index
Edge counter without reset on index pulse. The counter is initialized on 0 and will count to a maximum of 65536 pulses. If maximum number of pulses is exceeded counter will continue to count from 0.
Edge counter input pin: EDGE?_CNTR
Edge counter reset on positive edge
Edge counter with reset on negative edge on EDGE?_I. Counter is initialized on 0 and will count to a maximum of 65536 pulses. If maximum number of pulses is exceeded counter will continue to count from 0. If a positive edge is received the
counter will be reset to zero.
Edge counter input pin: EDGE?_CNTR
Index input pin: EDGE?_I
Edge counter reset on negative edge
Edge counter with reset on negative edge on EDGE?_I. Counter is initialized on 0 and will count to a maximum of 65536
pulses. If maximum number of pulses is exceeded counter will continue to count from 0. If negative edge is received the
counter will be reset to zero.
Edge counter input pin: EDGE?_CNTR
Index input pin: EDGE?_I
Only available when the pins are not used for special function I/O.
16 Digital Inputs
Digital Input Pin: 3.3V is a logical 1, 0V is a logical 0.
Each pin can be individually selected as digital input, digital output
Corresponding value in 20-sim 4C will be either 0.0 or 1.0.
8x on pins: XDIO1_0 ... XDIO1_7
8x on pins: XDIO2_0 ... XDIO2_7
PWM
Pulse Width Modulation output (2x)
The frequency is set to 20kHz.
The duty cycle can be specified in 20-sim 4C between [-1.0 , 1.0] (i.e. 0.5 = 50% dutycycle) and is available at pin PWM?_DUTY
The sign sets the direction. Positive sign: PWM?_nDIR = low and PWM?_pDIR = high. Negative sign: PWM?_nDIR = high and PWM?_pDIR = low.
When the value is zero PWM?_nDIR and PWM?_pDIR are set to low.
Stepper
Pulse frequency generation output (2x)
The pulse width is fixed to 80 {us}. Therefore the maximum pulse frequency is 6250 {Hz} (=1/160{us}).
The frequency can be specified in 20-sim 4C between [-6250.0, 6250.0] and is available at pin STEPPER?_PULSE
The sign sets the direction. Positive sign: STEPPER?_nDIR = low and STEPPER?_pDIR = high. Negative sign: STEPPER?_nDIR = high and STEPPER?_pDIR = low.
No pulses are generated when the frequency value is smaller than 5.0 (5 {Hz}) due to limitations in the pulse generator. STEPPER?, STEPPER?_nDIR and STEPPER?_pDIR are set to low.
Only available when the pins are not used for special function I/O.
15 Digital Outputs
Digital Output Pin: A value > 0.0 sets the output to 3.3V and 0.0 sets the output to 0 V
Each pin can be individually selected as digital input, digital output
8x on pins: XDIO1_0 ... XDIO1_7
7x on pins: XDIO2_0, XDIO2_2, XDIO2_3, XDIO2_4, XDIO2_5, XDIO2_6, XDIO2_7 (XDIO2_1 is not available as output)